(1) Field of the Invention
The invention relates to a method to fabricate an integrated circuit device, and, more particularly, to a method to form very narrowly-spaced polysilicon lines in the manufacture of an integrated circuit device.
(2) Description of the Prior Art
Non-volatile memories are widely used in the art of electronics. Non-volatile memories, such as EEPROM and flash EEPROM, hold memory states even in the absence of a power supply while providing re-programmability. Typical non-volatile memory devices use a complex gate comprising a control gate and a floating gate. The control gate acts in similar fashion to a standard, MOS gate to control the channel-state (ON/OFF) of the transistor. The floating gate acts a charge storage structure. The relative charge-state of the floating gate controls the relative threshold voltage of the device. The device is constructed such that biases on the control gate, source, and drain will cause charge movement onto or off from the floating gate to thereby program or erase the device. Another set of biases on the control gate, source, and drain is used to read the state of cell (‘0’or ‘1’).
The memory device manufacturer strives to improve the performance and to reduce the cost of the non-volatile memory. To this end, much effort has been put forth to improve the coupling ratio between the control gate and floating gate to thereby reduce the programming and/or erasing speed. Much effort has been expended to reduce the size of each memory cell and the size of the array. Many novel devices and configurations have been reported in the art. In addition, advances in lithography technology allow smaller feature widths and spacings to be formed on the integrated circuit and to create more densely packed memory arrays.
Referring now to FIG. 1, a small part of a partially fabricated, non-volatile array 10 is shown in top view. The array 10 comprises EEPROM cells each comprising a single floating gate (FG) 30a, 30b, 30c, and 30d. Wordlines 26a and 26b run in columns and form the control gates for devices along those columns. The sources 18 and drains 22 of the devices run along the row directions. The sources 18 in a column are typically tied together in a source line by a metal layer, not shown. The drains 22 in a column are typically tied together as a bit line by a metal layer, also not shown. Split gate devices, where the control gate (wordline) overlies a part of the channel, are shown.
Of particular importance to the present invention and as shown in the example, the features are fabricated to minimal dimensions. The active areas (OD) in the substrate, where the device drain 22, source 18, and gates 26 and 30 are formed, are separated by isolation regions 14. In this case, the isolation regions are formed as shallow trench isolation (STI) regions 14. The STI regions 14 are formed at a minimal width and spacing. The STI region spacing is shown by dimension B. The floating gates 30a–30d, are designed at a width A1 that is somewhat smaller than the STI spacing B. By designing the FG width A smaller than the STI spacing B, a self-aligned floating gate is achieved.
Referring now to FIG. 2, a cross section of the memory array is shown. The STI regions 14 are formed as trenches filled with dielectric material 14 in the semiconductor substrate 12. The floating gates comprise a conductor layer 30, such as polysilicon, overlying a gate dielectric layer 28. The conductor layer 30 is formed as a conformal film overlying the gate dielectric layer 28 and the STI regions 14. Then the conductor layer 30 is patterned using a lithographic technique as is well known in the art. Because, the floating gate mask is made somewhat smaller than the STI spacing, the resulting floating gates 30 are formed between, but not overlying, the protruding STI dielectric material 14. This can result in a problem, however, because OD trenches 38 can be formed between the floating gates 30 and the STI regions 14. These trenches present gap-filling problems for subsequently deposited dielectric films and can cause device or floating gate leakage.
Referring now to FIG. 3, the prior art memory array 40 is again shown in top view. In this case, however, a non-self-aligned floating gate scheme is used. The floating gates 44a–44d are designed to have widths A2 greater than the STI spacing B. This design choice means that the floating gates 44a–44d will have edges on the STI regions 14 such that the OD trench problem does not occur. However, the resulting space C′ between the floating gates 44a–44d is less than the minimum width C of the STI region 14. Therefore, this non-self-aligned floating gate would require more precise, and expensive, photolithography and etching processes than in the self-aligned case.
To create these very narrowly-spaced floating gates 44a–44d, without increasing the photolithography process expense, a spacer-based hard mask has been used in the prior art. Referring now to FIG. 4a, the memory array integrated circuit is shown in cross section. Again, the conductor layer 44 is formed overlying the gate dielectric layer 28 and the STI regions 14. A hard mask layer 48 is deposited overlying the conductor layer 44. The hard mask layer 48 is then patterned to form masking polygons overlying the conductor layer 44 where the floating gates are planned. Note that the hard mask layer 48 is patterned with the larger spacings C corresponding to the STI region 14 spacings B. In this way, the hard mask patterning does not require more precise and expensive photolithography.
Referring now to FIG. 4B, spacers 52 are formed on the sidewalls of the hard mask layer 48 by, for example, depositing a film 52 and then anisotropically etching the film to remove it from the horizontal surfaces while leaving the spacers 52 on the vertical surfaces. Note that the spacers 52 increase the effective width of the hard mask 48 such that the combined masking polygons 48 and 52 have smaller spaces C′. These smaller spaces C′ are achieved without a second photolithography process sequence. Referring now to FIG. 4C, the conductor layer 44 is etched through where exposed by the masking polygons 48 and 52 to complete the floating gates 44. The smaller spaces C′ between the floating gates 44 are thereby achieved. While the approach does not require an expensive photolithography process, it does have the disadvantage of adding the sidewall spacer process, which includes a deposition and an etch, to the overall process flow.
Several prior art inventions relate to integrated circuit manufacturing, in general, and to nonvolatile memory device manufacture in particular. U.S. Pat. No. 6,342,451 B1 to Ahn discloses methods to form a floating gate. Sidewall spacers are used to define a floating gate pattern. U.S. Pat. No. 6,514,868 B1 to Hui et al teaches a method to form a contact hole. A tapered hard mask is used to define a contact hole opening. U.S. Pat. No. 6,177,331 B1 to Koga teaches an integrated circuit manufacturing method where a hard mask is tapered.